This patent application claims priority to French Patent Application Number 01 09190 filed on Jul. 11, 2001.
The invention relates to a clock circuit protected against voltage or current spikes. The invention relates especially to any integrated circuit of which at least one element uses a clock signal for its operation, such as for example (but not exclusively) flip-flop type circuits, latch type circuits or, more generally, logic circuits using a clock signal.
The constant and gradual miniaturization of electronic circuits is giving rise to increasingly efficient and ever smaller circuits. This means, however, that the circuits are becoming increasingly sensitive to their environment and especially to logic random events caused by an additional supply of energy from outside the circuit.
A logic random event is a specific change in state or a transitional state (voltage and/or current spike) at the point of an integrated circuit. By definition, a random event is unpredictable or hardly predictable. Logic random events may have different origins.
A logic random event is induced, for example, by the impinging of a charged energy article on a point of an integrated circuit. A random factor of this time is known as a xe2x80x9csingle event upsetxe2x80x9d or SEU. This type of random event appears in integrated circuits used for space applications, because of radiation encountered outside the earth""s protective atmospheric and magnetospheric layers. This type of random event is also increasingly frequent in integrated circuits for terrestrial applications, especially for the finer technologies such as the 0.25 xcexcm, 0.18 xcexcm and 0.12 xcexcm technologies.
A logic random event may also be induced by localized capacitive coupling between two layers of one and the same integrated circuit. In this case, the term xe2x80x9cglitchxe2x80x9d is often used.
A random event, whatever its cause, is generally expressed by a voltage and/or current spike on a digital or analog signal at a disturbed point of the circuit (a point of impingement in the case of an SEU, a coupling point in the case of a glitch, etc.).
If C denotes the equivalent capacitance of the circuit downstream from the disturbed point of the circuit, then the variation in voltage xcex94V at the disturbed point considered is written xcex94V=xcex94Q/C, xcex94Q being the variation in charge resulting from the impingement or the coupling.
A random event may have consequences of varying importance for the circuit that it disturbs.
For example, for a downstream circuit using only logic signals, if the voltage variation xcex94V is small enough to cause no change in the state of the disturbed logic signal, then the disturbance disappears in a fairly short time without any consequence for the downstream circuit.
If, on the contrary, the voltage variation xcex94V is greater, and especially if it is sufficient to modify the value of the logic signal, then the consequences may be great: a random event may thus cause an inverter to switch over or a SRAM type memory cell to get reprogrammed etc.
The clock circuit of an integrated circuit is generally constituted (FIG. 1) by a tree-like structure comprising different arms 111 to 117 enabling the supply, by a single initial CI, of all the elements 121 to 128 of the integrated circuit. Buffers (most usually inverter amplifiers) 131 to 139 are generally placed along the different arms of the clock circuit in order to control firstly the reductions in the level of the signal due to losses along the arms and, secondly, phase differences generated by the different lengths of arms.
The consequences of a random event on a circuit such as the clock circuit may be great since it may disturb several elements of the circuit simultaneously, depending on the arm of the clock circuit on which the random event appears. Indeed, a random event on an arm of the clock circuit may cause for example a switching or dual switching of the clock signal supplying one or more elements of the integrated circuit. A first consequence thereof is that these elements get desynchronized from the other elements of the integrated circuit. A second consequence is that the downstream circuits could be modified: there could be a change in the state of a memory, a flip-flop circuit etc.
In practice, for a buffer located far upstream from the clock circuit, for example the buffer 131, the capacitive charge at output of this buffer is great because it is constituted by the sum of the capacitive charges of the circuits downstream from the buffer considered. Consequently, a random event appearing at the input of an upstream buffer does not disturb the downstream circuits because the associated variation in voltage xcex94V is low or even very low, the capacitive charge C being high.
On the contrary, for a buffer located far downstream from the clock circuit or even at the input of an element of the integrated circuit, such as for example the buffers 134, 125, the resulting capacitive charge C is low. Therefore, a random event appearing at the input of a downstream buffer is transmitted to the output of this buffer, and it is liable to disturb the working of the downstream circuit or circuits if they are not protected.
It is therefore indispensable to protect the clock circuit of an integrated circuit to prevent any disturbance of the downstream circuits using the clock signal.
It is an object of the invention to propose a circuit for protection against random events.
It is another object of the invention to propose a clock circuit using a protection circuit of this kind.
It is also an object of the invention to propose a clock circuit producing identical or inverse synchronous clock signals to limit the risk of the cumulative disturbance of several signals simultaneously.
With these goals in view, the invention relates to a protection circuit to receive an initial clock signal and send at least one resultant clock signal to a downstream circuit.
According to the invention, the protection circuit comprises:
an input circuit receiving the initial clock signal and producing two intermediate clock signals that are images of the initial clock signal,
a recombination circuit to give a first resulting clock signal that is:
the image of the intermediate signals if said intermediate signals are identical, or
inactive if the intermediate signals are different from each other.
The term xe2x80x9cinactive signalxe2x80x9d should be understood here to be a signal that does not disturb a downstream circuit, the output of the recombination circuit that produces it being, in this case, a high-impedance circuit.
The invention also relates to a clock circuit for an integrated circuit comprising a protection circuit such as the one described here above.
Thus, if a random event disturbs the working of the protection circuit according to the invention, then an inactive clock signal is given at output of the protection circuit. The disturbance is not transmitted to the downstream circuit: the operation of the downstream circuit is blocked for a few instants until the disappearance of the disturbance. There is therefore no risk of an undesired operation of the downstream circuit.
Preferably, the protection circuit is connected between a downstream circuit using a clock signal and the end of an arm of the clock circuit giving the clock signal to the downstream circuit. The point of the clock circuit most sensitive to the random events is thus protected.
The input circuit used for the protection circuit according to the invention comprises:
a first buffer comprising an input to which the initial clock signal is applied, and an output to give one of the intermediate clock signals,
a second buffer comprising an input connected to the input of the first buffer and an output to give the other one of the intermediate signals.
The input circuit thus separates the initial clock signal into two intermediate clock signals which are identical in normal operation of the circuit. The first buffer and second buffer are preferably distant from each other in the drawing of the circuit. Thus the same random event cannot simultaneously disturb both buffers. Thus, if a random event disturbs the circuit then only one of the intermediate clock signals is liable to be disturbed.
The recombination circuit of the protection circuit that is an object of the invention, for its part, comprises a first complex inverter comprising a first input and a second input to receive respectively both of the intermediate signals, and an output at which the first resultant clock signal is given. As will be seen more clearly hereinafter in a description of an exemplary embodiment, the first complex inverter produces a first resultant clock signal which is:
the inverse of the intermediate clock signals when these signals are identical,
inactive (or at high impedance) if they are different.
Thus, a disturbance appearing at one of the intermediate signals is not transmitted to the resultant signal, which is momentarily inactive. The term xe2x80x9cinactive signalxe2x80x9d must be understood here to mean a signal that does not disturb a downstream circuit. In practice here, when the intermediate clock signals are different, the first complex inverter is off so that its output is at high impedance: the resultant signal is thus kept at its previous value because of the presence of a low capacitance at output of the first inverter, which is inherent in the inverter.
According to a preferred embodiment of the invention, the recombination circuit also comprises a second complex inverter, comprising a first input and a second input to respectively receive both the intermediate signals, and an output at which a second resultant clock signal is given.
The first and second complex inverters are preferably identical, so that the first resultant signal and second resultant signal are identical if the protection circuit is not disturbed by a random event. If, on the contrary, a disturbance appears then it disturbs only one of the two resultant signals and the other one can be used by the downstream circuit.
Preferably again, as a complement to the first complex inverter and the second complex inverter, the recombination circuit comprises a third complex inverter, comprising a first input and a second input to respectively receive the first resultant clock signal and the second resultant clock signal, and an output at which a third resultant clock signal is given.
The third resultant clock signal is:
the inverse of the first resultant signal if the first resultant signal and the second resultant signal are identical,
inactive if not.
According to this embodiment, in normal operation, there are thus three signals available at output of the protection circuit, the third signal being complementary to the first two. If, on the contrary, the circuit is disturbed, then at most two of the resultant signals are at high impedance, and the third one therefore remains available.
According to another embodiment, as a complement to the first complex inverter and the second complex inverter, the recombination circuit comprises a first simple inverter comprising an input to receive the first resultant clock signal and an output at which the third resultant clock signal is given, the first simple inverter also comprising:
a fifth P type transistor receiving a power supply voltage at a source, and
a sixth N type transistor, a drain of which is connected to a drain of the fifth transistor, and a source of which is connected to the ground of the circuit,
a gate of the fifth transistor and a gate of the sixth transistor being connected together to the input of the first simple inverter, the common drain of the fifth transistor and of the sixth transistor being connected to the output of the first simple inverter.
The recombination circuit also preferably comprises a second simple inverter comprising an input to receive the second resultant clock signal and an output at which a fourth resultant clock signal is given.
According to this embodiment, there are four resultant clock signals available at output of the recombination circuit. In normal operation, they are identical in sets of two. If, on the contrary, a random event appears, then only a restricted number of output signals is inactive. The other output signals can be used is by the downstream circuit.